IEEE 1838-2019 pdf free.IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits.
Like all micro-electronic products, these die stacks need to be tested before they can be shipped with acceptable quality levels to their customers. We distinguish the following tests: (I) pie-bond tests prior to stacking. (2) nsid-hond tests on incomplete, partial stacks. (3)post-hond tests on complete yet not packaged stacks, and (4) final tests on the final packaged product. The number of possible test flows grows quickly with the number of dies in the stack and hence is subject of automated trade-oflevaluation and optimization (see, IHl , [4I. and IRS I).
1.3 MotivatIon for a 3D-DfT standard
A well-architected DIT access infrastructure is indispensable for achieving a high-quality test. Not only do we need conventional 2D-DtT structures (such as internal scan chains, test data compression circuitry, IEEE Std 1500 wrappers around embedded cores, andor built-in self-test (BIST) engines) that provide test access within a single die, we also need new approaches for testing stacked systems. Especially once a (partial or complete) vertical stack has been formed(i.e., in mid-bond, post-bond, or final testing phases), we also need novel 3D-DIT structures that provide test access from (and to) the external stack I/Os to (and from) the various dies and inter-die interconnects. For example: if a stack consists of three dies and test access from external test equipment is exclu.sively possible via the stack lOs that are concentrated in, say, Die I, then Die I and Die 2 need to cooperate in transporting test stimuli and responses up and down the stack in order to be able to test Die 3.
To enable separation of the test development as well as test execution for the various dies in the stack, the 3 D-DIT architecture should enable modular testing, i.e., tests for dies and interconnect layers between adjacent stacked dies can be developed and executed individually. Several ad-hoc 3D-DtT architectures have been proposed, among others based on IEEE Std 1149. I, IEEE Std 1500, and IEEE Std 1687. These architectures all have their specific strong and weak points. However, these ad-hoc 3D.Dfl’ architectures do hot inter-operate together. Hence, there is a need for a per-die 3D-DIT standard, such that if compliant dies (even if designed and developed by different teams or different companies) are brought together in a die stack, a basic minimum of test features should work across the stack. This is exactly the aim of IEEE Std 1838.
1.4 Context
The Standard for Test Access Architecture for Three-I)imensional Stacked ICs is conceptually related to previously developed design-for-test (Dfr) standards, in particular IEEE Sid 1149.1. IEEE Std 1500. and IEEE Std 1687. The first two standards specify test access architectures for ICs on boards (lElili Std 1149.1) and IP cores embedded within an K’ (IEEE Std 1500). IEEE Std 1687 describes an access architecture to embedded instruments. These three previously developed standards have influenced and are referred to in this standard, so a solid understanding of these standards is strongly recommended.IEEE 1838 pdf download.
IEEE 1838-2019 pdf free
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