BS EN IEC 63093-9:2020 pdf free.Ferrite cores – Guidelines on dimensions and the limits of surface irregularities Planar cores.
The areas of the chips located on the mating surfaces (C1 and C1’irregularities in Figure 7 Figure 8 and Figure 9) shall not exceed the following limits:
the cumulative area of the chips shall be less than 4 % of the relevant mating surface.The mating surface of each outer leg and centre post is considered separately.The minimum area is taken as 0,5 mm2 to be distinguishable to the naked eye; the total length of the ragged edges shall be less than 25 % of the perimeter of therelevant mating surface.
For chips and ragged edges located on the surfaces:
the allowable chipping areas are doubled as compared to the limits for the whole mating surfaces;
the total length of the ragged edges shall be less than 25 % of the perimeter of the smalleradjoining surface;
chips and ragged edges are not acceptable on the inner edges of the wire slot area(C2 irregularity in Figure 8 and Figure 9).Area and length reference for visual inspection are given in Table 7.Reference values ofallowable areas of chips are given in Annex B.
Different cracks are shown in Figure 10,Figure 11 and Figure 12. In principle three differenttypes of cracks can be distinguished.
a) Cracks which are parallel to the magnetic flux path(S1,S2,S5,S5’,S5′).These cracks are magnetically not critical.The maximum length of a single crack is 33 % (1/3) of thedimension of the relevant surface which is parallel to the crack. In the case of multiplecracks the maximum cumulative length doubles.
b) Cracks which are perpendicular to the magnetic flux path (S3,S3′,S3″,S4,S4′). These cracks are magnetically critical. They can reduce the relative cross-section of themagnetic flux or add an additional air gap into the magnetic circuit.The maximum totallength of cracks is 20 % (1/5) of the dimension of the relevant surface which is parallel tothe crack.
c) Cracks which go from one edge to another edge (S6). These cracks can cause chipping during the operation in the circuit. The loose particles can cause malfunctions in the circuit.Therefore this type of crack is not acceptable in any case.
The reference dimensions are given in Figure 13,Figure 14 and Figure 15.
The limits for cracks are given in Table 8,Table 9 and Table 10.
There shall be no flash extending from the core into the wire slot.
The pull-outs are applicable only for the inner surface where the PCB is seated (as shown inFigure 10,Figure 11 and Figure 12).
For planar EL-cores, low-profile E-cores and low-profile ER-cores, the cumulative area of pul-outs of the core shall be less than 20 % of the total respective surface area.BS EN IEC 63093-9 pdf download.